參數(shù)資料
型號(hào): 74VHC132T
廠商: 意法半導(dǎo)體
英文描述: Quadruple 2-Input Exclusive-OR Gates 14-TSSOP -40 to 85
中文描述: 四2輸入施密特與非門(mén)
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 53K
代理商: 74VHC132T
74VHC132
QUAD 2-INPUT SCHMITT NAND GATE
PRELIMINARY DATA
June 1999
I
HIGHSPEED:t
PD
=4.9ns(TYP.)atV
CC
= 5V
I
LOWPOWERDISSIPATION:
I
CC
=2
μ
A(MAX.) at T
A
=25
o
C
I
TYPICALHYSTERESIS:V
h
= 1V atV
CC
= 4.5V
I
POWERDOWN PROTECTIONON INPUTS
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 8 mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES132
I
IMPROVEDLATCH-UP IMMUNITY
I
LOWNOISE:V
OLP
= 0.8V(Max.)
DESCRIPTION
The 74VHC132 is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
and
regard to the supply voltage. This device can be
used to interface5V to 3V.
Pin configuration and function are the same as
those of the VHC00 but the VHC132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74VHC132M
74VHC132T
M
(Micro Package)
T
(TSSOPPackage)
1/7
相關(guān)PDF資料
PDF描述
74VHC132M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC132 Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC132M Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
74VHC132MTC Quadruple 2-Input Exclusive-OR Gates 14-PDIP -40 to 85
74VHC132MTCX Quadruple 2-Input Exclusive-OR Gates 14-SO -40 to 85
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