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參數(shù)資料
| 型號(hào)： | 74V2G74 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR |
| 中文描述： | 單一的D型觸發(fā)器與預(yù)置和清除 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 289K |
| 代理商： | 74V2G74 |
74V2G74
5/13
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
15
6.7
11.9
1.0
14.0
1.0
14.0
ns
50
9.2
15.4
1.0
17.5
1.0
17.5
15
4.6
7.3
1.0
8.5
1.0
8.5
50
6.1
9.3
1.0
10.5
1.0
10.5
t
PLH
t
PHL
Propagation Delay
Time PR or CLR to
Q or Q
15
7.6
12.3
1.0
14.5
1.0
14.5
ns
50
10.1
15.8
1.0
18.0
1.0
18.0
15
4.8
7.7
1.0
9.0
1.0
9.0
50
6.3
9.7
1.0
11.0
1.0
11.0
t
W
CK Pulse Width
HIGH or LOW
6.0
7.0
7.0
ns
5.0
5.0
5.0
t
W
PR or CLR Pulse
Width LOW
6.0
7.0
7.0
ns
5.0
5.0
5.0
t
s
Setup Time D to CK
HIGH or LOW
6.0
7.0
7.0
ns
5.0
5.0
5.0
t
h
Hold Time D to CK
HIGH or LOW
0.5
0.5
0.5
ns
0.5
0.5
0.5
t
REM
Removal Time
PR or CLR to CK
5.0
5.0
5.0
ns
3.0
3.0
3.0
f
MAX
Maximum Clock
Frequency
15
80
125
70
70
MHz
50
50
75
45
45
15
130
170
110
110
50
90
115
75
75
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
3.3
4
10
10
10
pF
3.3
f
IN
= 10MHz
22
pF
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