參數(shù)資料
型號(hào): 74V2G74
廠商: 意法半導(dǎo)體
英文描述: SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR
中文描述: 單一的D型觸發(fā)器與預(yù)置和清除
文件頁(yè)數(shù): 1/13頁(yè)
文件大?。?/td> 289K
代理商: 74V2G74
1/13
December 2001
I
HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
I
LOW POWER DISSIPATION:
I
CC
= 1
μ
A (MAX.) at T
A
=25°C
I
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
I
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
I
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
I
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
I
FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
I
I
DESCRIPTION
The 74V2G74 is an advanced high-speed CMOS
SINGLE D-TYPE FLIP FLOP WITH PRESET
AND CLEAR fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
tecnology.
A signal on the D INPUT is transfered to the Q and
Q OUTPUTS during the positive going transition
of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
74V2G74
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
T & R
SOT23-8L
SOT323-8L
74V2G70STR
74V2G70CTR
SOT23-8L
SOT323-8L
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