參數(shù)資料
型號: 74LVX27TTR
廠商: 意法半導體
英文描述: LEVER FOR SELECTOR SWITCH 22MM
中文描述: 低電壓CMOS三重3輸入或非門,與5V容限輸入
文件頁數(shù): 4/8頁
文件大?。?/td> 128K
代理商: 74LVX27TTR
74LVX27
4/8
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/3 (per gate)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
2.7
3.3
(*)
3.3
(*)
2.7
3.3
(*)
15
50
15
5.2
8.0
4.1
8.6
13.5
6.2
1.0
1.0
1.0
10.5
15.4
7.5
1.0
1.0
1.0
12.0
17.0
9.0
ns
50
50
6.6
0.5
0.5
9.7
1.0
1.0
1.0
11.0
1.5
1.5
1.0
12.5
1.5
1.5
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
ns
50
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
3.3
4
10
10
10
pF
3.3
19
pF
相關PDF資料
PDF描述
74LVX27MTR LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
74LVX27 LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
74LVX27M LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
74LVX3245TTR OCTAL DUAL SUPPLY BUS TRANSCEIVER
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