參數(shù)資料
型號(hào): 74LVX27MTR
廠商: 意法半導(dǎo)體
英文描述: LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
中文描述: 低電壓CMOS三重3輸入或非門,與5V容限輸入
文件頁數(shù): 1/8頁
文件大?。?/td> 128K
代理商: 74LVX27MTR
1/8
July 2001
I
HIGH SPEED :
t
PD
= 4.1ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL :
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
μ
A (MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 27
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
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I
I
I
I
I
I
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DESCRIPTION
The 74LVX27 is a low voltage CMOS TRIPLE
3-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX27
LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74LVX27M
74LVX27MTR
74LVX27TTR
TSSOP
SOP
相關(guān)PDF資料
PDF描述
74LVX27 LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
74LVX27M LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
74LVX3245TTR OCTAL DUAL SUPPLY BUS TRANSCEIVER
74LVX3245M OCTAL DUAL SUPPLY BUS TRANSCEIVER
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