參數(shù)資料
型號(hào): 74LVC161PW,112
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 17/22頁(yè)
文件大?。?/td> 0K
描述: IC SYNC 4BIT BIN COUNTER 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 96
系列: 74LVC
邏輯類(lèi)型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 150MHz
觸發(fā)器類(lèi)型: 正邊沿
電源電壓: 1.2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
其它名稱(chēng): 74LVC161PW
74LVC161PW-ND
935210530112
74LVC161
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 30 September 2013
4 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
5.
Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO16 and (T)SSOP16
Fig 6.
Pin configuration for DHVQFN16
161
MR
VCC
CP
TC
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CEP
CET
GND
PE
001aad086
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aad087
161
CEP
CET
D3
Q3
D2
Q2
D1
Q1
D0
Q0
CP
TC
GND(1)
GND
PE
MR
V
CC
Transparent top view
7
10
6
11
5
12
4
13
3
14
2
15
8
9
1
16
terminal 1
index area
Table 2.
Pin description
Symbol
Pin
Description
MR
1
synchronous master reset (active LOW)
CP
2
clock input (LOW-to-HIGH, edge-triggered)
D[0:3]
3, 4, 5, 6
data input
CEP
7
count enable input
GND
8
ground (0 V)
PE
9
parallel enable input (active LOW)
CET
10
count enable carry input
Q[0:3]
14, 13, 12, 11
flip-flop output
TC
15
terminal count output
VCC
16
supply voltage
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