參數(shù)資料
型號: 74HC4046AD/T3
廠商: NXP SEMICONDUCTORS
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, PDSO16
封裝: SOT-109, SOP-16
文件頁數(shù): 18/34頁
文件大?。?/td> 442K
代理商: 74HC4046AD/T3
1997 Nov 25
25
Philips Semiconductors
Product specication
Phase-locked-loop with VCO
74HC/HCT4046A
APPLICATION INFORMATION
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT4046A
in a phase-lock-loop system.
References should be made to Figs 29, 30 and 31 as indicated in the table.
Values of the selected components should be within the following ranges:
R1
between 3 k
and 300 k;
R2
between 3 k
and 300 k;
R1 + R2 parallel value
> 2.7 k;
C1
greater than 40 pF.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
VCO frequency characteristic
VCO frequency
without extra
offset
PC1, PC2 or PC3
With R2 =
∞ and R1 within the range 3 k< R1 < 300 k, the
characteristics of the VCO operation will be as shown in Fig.25.
(Due to R1, C1 time constant a small offset remains when R2 =
∞.).
Fig.25 Frequency characteristic of VCO operating without offset:
f0 = centre frequency; 2fL = frequency lock range.
Selection of R1 and C1
PC1
Given fo, determine the values of R1 and C1 using Fig.29.
PC2 or PC3
Given fmax and fo, determine the values of R1 and C1 using Fig.29, use
Fig.31 to obtain 2fL and then use this to calculate fmin.
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