參數(shù)資料
型號(hào): 74HC40103DB,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 3/25頁(yè)
文件大?。?/td> 0K
描述: IC 8BIT SYNC BINARY DOWN 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 32MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 568-8880-2
74HC40103DB,118-ND
74HC40103DB-T
74HC40103DB-T-ND
935189340118
9397 750 13812
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
11 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
tW
CP clock pulse width HIGH or
LOW
VCC = 2.0 V
165
22
-
ns
VCC = 4.5 V
33
8
-
ns
VCC = 6.0 V
28
6
-
ns
MR master reset pulse width
LOW
VCC = 2.0 V
125
39
-
ns
VCC = 4.5 V
25
14
-
ns
VCC = 6.0 V
21
11
-
ns
PL preset enable pulse width
LOW
VCC = 2.0 V
125
33
-
ns
VCC = 4.5 V
25
12
-
ns
VCC = 6.0 V
21
10
-
ns
trem
removal time MR to CP, PL to CP
VCC = 2.0 V
50
14
-
ns
VCC = 4.5 V
10
5
-
ns
VCC = 6.0 V
9
4
-
ns
tsu
set-up time PE to CP
VCC = 2.0 V
75
22
-
ns
VCC = 4.5 V
15
8
-
ns
VCC = 6.0 V
13
6
-
ns
set-up time TE to CP
VCC = 2.0 V
150
44
-
ns
VCC = 4.5 V
30
16
-
ns
VCC = 6.0 V
26
13
-
ns
set-up time Pn to CP
VCC = 2.0 V
75
22
-
ns
VCC = 4.5 V
15
8
-
ns
VCC = 6.0 V
13
6
-
ns
th
hold time PE to CP
VCC = 2.0 V
0
14
-
ns
VCC = 4.5 V
0
5-
ns
VCC = 6.0 V
0
4-
ns
hold time TE to CP
VCC = 2.0 V
0
30
-
ns
VCC = 4.5 V
0
11
-
ns
VCC = 6.0 V
0
9-
ns
hold time Pn to CP
VCC = 2.0 V
0
17
-
ns
VCC = 4.5 V
0
6-
ns
VCC = 6.0 V
0
5-
ns
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr =tf = 6 ns; CL = 50 pF; see Figure 13.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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