參數(shù)資料
型號: 74HC40103DB,118
廠商: NXP Semiconductors
文件頁數(shù): 12/25頁
文件大?。?/td> 0K
描述: IC 8BIT SYNC BINARY DOWN 16SSOP
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 2,000
系列: 74HC
邏輯類型: 二進制計數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 8
復位: 異步
計時: 同步
計數(shù)速率: 32MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 568-8880-2
74HC40103DB,118-ND
74HC40103DB-T
74HC40103DB-T-ND
935189340118
9397 750 13812
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
2.
Features
s Cascadable
s Synchronous or asynchronous preset
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specied from
40 °Cto+80 °C and from 40 °C to +125 °C.
3.
Applications
s Divide-by-n counters
s Programmable timers
s Interrupt timers
s Cycle/program counters.
4.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
Table 1:
Quick reference data
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH
propagation delay CP to TC CL = 15 pF;
VCC = 5 V
-30
-
ns
fmax
maximum clock frequency
CL = 15 pF;
VCC = 5 V
-
32
-
MHz
CI
input capacitance
-
3.5
-
pF
CPD
power dissipation
capacitance
VI = GND to VCC
[1] -24
-
pF
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