參數(shù)資料
型號(hào): 74HC193DB,118
廠商: NXP Semiconductors
文件頁(yè)數(shù): 7/30頁(yè)
文件大?。?/td> 0K
描述: IC 4BIT BINAR UP/DN COUNT 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 74HC193DB-T
74HC193DB-T-ND
935188610118
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
15 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
[1]
tpd is the same as tPHL and tPLH.
[2]
CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(C
L VCC
2
f
o) = sum of outputs.
tsu
set-up time
Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC =4.5 V
16
8
-
20
-
24
-
ns
VCC =6.0 V
14
6
-
17
-
20
-
ns
th
hold time
Dn to PL; see
VCC =2.0 V
0
14
-
0
-
0
-
ns
VCC =4.5 V
0
5-
0
-
0
-
ns
VCC =6.0 V
0
4-
0
-
ns
CPU to CPD,
CPD to CPU; see
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC =4.5 V
16
8
-
20
-
24
-
ns
VCC =6.0 V
8
6
-
17
-
20
-
ns
fmax
maximum
frequency
CPU, CPD; see
VCC = 2.0 V
4.0
13.5
-
3.2
-
2.6
-
MHz
VCC =4.5 V
20
41
-
16
-
13
-
MHz
VCC =6.0 V
24
49
-
19
-
15
-
MHz
CPD
power
dissipation
capacitance
VI = GND to VCC;
VCC =5V;
fi =1 MHz
-24-
-
pF
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol
Parameter
Conditions
25
C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
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