參數(shù)資料
型號: 74HC193DB,118
廠商: NXP Semiconductors
文件頁數(shù): 11/30頁
文件大?。?/td> 0K
描述: IC 4BIT BINAR UP/DN COUNT 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類型: 二進(jìn)制計數(shù)器
方向: 上,下
元件數(shù): 1
每個元件的位元數(shù): 4
復(fù)位: 異步
計時: 同步
計數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 74HC193DB-T
74HC193DB-T-ND
935188610118
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
19 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
001aag415
Dn input
VI
GND
VI
GND
VI
GND
VOH
VOL
Qn output
CPU, CPD
input
PL input
VM
tW
trec
tPLH
tPHL
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
001aag416
MR input
Qn output
VOH
VOL
VI
GND
VI
GND
CPU, CPD
input
VM
10 %
90 %
trec
tPHL
tTHL
tW
tTLH
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