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參數(shù)資料
| 型號： | 74F807 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal shift/count registered transceiver with adder and parity 3.State |
| 中文描述： | 八進制移位/罪名加法器和奇偶3.State登記收發(fā)器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 72K |
| 代理商： | 74F807 |
Philips Semiconductors FAST Products
Product specification
FAST 74F807
Octal shift/count registered transceiver
with adder and parity (3–State)
June 18, 1991
2
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
An, Bn
Data I/O inputs
3.5/0.166
70
μ
A/70
μ
A
OEA, OEB
A output enable inputs
1.0/0.033
20
μ
A/20
μ
A
CI/SI/CE
Carry in/serial in/clock enable input
1.0/0.033
20
μ
A/20
μ
A
CP
Clock input
1.0/0.033
20
μ
A/20
μ
A
MR
Master reset input (active low)
1.0/0.033
20
μ
A/20
μ
A
Sn
Select inputs
1.0/0.033
20
μ
A/20
μ
A
STATOUT
Status out output
150/40
3mA/24mA
An, Bn
Data I/O outputs
150/40
3mA/24mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
PIN CONFIGURATION PLCC
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
19
20
21
22
23
24
25
26
27
28
OEA
OEB
A0
A1
A2
A3
GND
GND
A4
A5
A6
A7
CI/SI/CE
CP
4
3
2
1
28
27
25
24
23
22
21
20
11
10
9
8
7
6
18
16
17
15
14
13
26
19
12
5
PLCC
A2
A3
GND
GND
A4
A5
A6
11
12
13
14
15
16
17
18
V
CC
OEA
A0
A1
MR
STAT
OUT B0
B7
S2
CP
CI/
SI/
CE
A7
MR
STATOUT
B0
B1
B2
B3
B4
B5
B6
B7
S0
S1
S2
OEB
S1
S0
B1
B2
B3
V
CC
B4
B5
B6
LOGIC SYMBOL
IEC/IEEE SYMBOL
2
1
EN3
3
4
5
8
9
10
11
13
13
17
16
15
14
28
1
2
26
25
24
23
21
20
19
18
R
EN1
EN2
0
3
M1
15
27
STATUS
OUT
OEA
OEB
CI/SI/CE
MR
V
= Pin 22
GND = Pin 7, 8
3
4
5
6
9
10
11
12
26
25
24
23 22
20 19
18
1
2
13
28
STATOUT
27
B0 B1 B2
B3 B4
B5 B6
B7
A0 A1 A2
A3 A4
A5 A6 A7
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