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參數(shù)資料
| 型號： | 74F648A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal transceiver/register, non-inverting(3-State)(八通道收發(fā)器/寄存器，同向（三態(tài)）) |
| 中文描述： | 八路收發(fā)器/寄存器，非反相（3態(tài)）（八通道收發(fā)器/寄存器，同向（三態(tài)）） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 121K |
| 代理商： | 74F648A |
Philips Semiconductors
Product specification
74F646/A/74F648/A
Transceivers/registers
2
1990 Sep 25
853-1124 00515
FEATURES
Combines 74F245 and two 74F374 type functions in one chip
High impedance base inputs for reduced loading (70
μ
A in high
and low states)
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Controlled ramp outputs for 74F646A/74F648A
3-state outputs
300 mil wide 24-pin slim dip package
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE is active low. In the
isolation mode (OE = high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
TYPICAL f
max
115MHz
TYPICAL SUPPLY CURRENT ( TOTAL)
74F646/74F648
140mA
74F646A/74F648A
185MHz
105mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F646N, N74F646AN, N74F648N, N74F648AN
PKG DWG #
24–pin plastic slim DIP
(300mil)
SOT222-1
24–pin plastic SOL
N74F646D, N74F646AD, N74F648D, N74F648AD
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
A0 – A7, B0 – B7
A and B inputs
3.5/0.116
70
μ
A/70
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
20
μ
A/20
μ
A
CPAB
A–to–B clock input
1.0/0.033
CPBA
B–to–A clock input
1.0/0.033
SAB
A–to–B select input
1.0/0.033
SBA
B–to–A select input
1.0/0.033
DIR
Data flow directional control enable input
1.0/0.033
OE
Output enable input
1.0/0.033
A0 – A7, B0 – B7
A, B outputs for N74F646A/N74F648A
750/80
15mA/48mA
A0 – A7, B0 – B7
NOTE:
One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
A, B outputs for N74F646/N74F648
750/106.7
15mA/64mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F649 | Octal transceiver/register, non-inverting open-collector |
| 74F647 | Octal transceiver/register, non-inverting open-collector |
| 74F64 | 4-2-3-2-input AND-OR-invert gate |
| 74F646MSAX | Single 8-bit Bus Transceiver |
| 74F646SCX | Single 8-bit Bus Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F648FCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transceiver/Register with TRI-STATE Outputs |
| 74F648FCX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transceiver/Register with TRI-STATE Outputs |
| 74F648FMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transceiver/Register with TRI-STATE Outputs |
| 74F648FMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transceiver/Register with TRI-STATE Outputs |
| 74F648LCQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Transceiver/Register with TRI-STATE Outputs |
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