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| 型號： | 74F632 |
| 英文描述： | 32-Bit Parallel Error Detection and Correction Circuit |
| 中文描述： | 32位并行錯誤檢測和校正電路 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 74F632 |
Functional Description
(Continued)
TABLE V. Syndrome Decoding
(Continued)
Syndrome Bits
Error
6
5
4
3
2
1
0
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
unc
unc
2-Bit
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
unc
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
DB
15
2-Bit
unc
DB
14
2-Bit
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
DB
13
2-Bit
DB
12
DB
11
2-Bit
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
DB
10
DB
9
2-Bit
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
DB
8
2-Bit
2-Bit
CB
5
Syndrome Bits
Error
6
5
4
3
2
1
0
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
unc
2-Bit
2-Bit
DB
23
2-Bit
DB
22
DB
21
2-Bit
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
2-Bit
DB
20
DB
19
2-Bit
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
DB
18
2-Bit
2-Bit
CB
4
2-Bit
DB
16
unc
2-Bit
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
DB
17
2-Bit
2-Bit
CB
3
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
unc (Note 1)
2-Bit
2-Bit
CB
2
2-Bit
CB
1
CB
0
None
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
CB
X
e
Error in check bit X
DB
Y
e
Error in data bit Y
2-Bit
e
Double-bit error
unc
e
Uncorrectable multi-bit error
Note:
2-bit and unc condition will cause both ERR and MERR to be LOW
Note 1:
Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs,
only ERR LOW for DB
30
error.
Note 2:
Syndrome bits for all HIGHs.
6
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