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參數(shù)資料
| 型號(hào)： | 74F632 |
| 英文描述： | 32-Bit Parallel Error Detection and Correction Circuit |
| 中文描述： | 32位并行錯(cuò)誤檢測(cè)和校正電路 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 74F632 |
Connection Diagram
(Continued)
Pin Assignment for
Side Brazed DIP
TL/F/9579–2
Order Number DP8406D (74F632DC)
See NS Package Number D52A
Functional Description
MEMORY WRITE CYCLE DETAILS
During a memory write cycle, the check bits (CB
0
through
CB
6
) are generated internally in the EDAC by seven 16-in-
put parity generators using the 32-bit data word as defined
in Table II. These seven check bits are stored in memory
along with the original 32-bit data word. This 32-bit word will
later be used in the memory read cycle for error detection
and correction.
ERROR DETECTION AND CORRECTION DETAILS
During a memory read cycle, the 7-bit check word is re-
trieved along with the actual data. In order to be able to
determine whether the data from memory is acceptable to
use as presented to the bus, the error flags must be tested
to determine if they are at the HIGH level.
The first case in Table III represents the normal, no-error
conditions. The EDAC presents HIGHs on both flags. The
next two cases of single-bit errors give a HIGH on MERR
and a LOW on ERR, which is the signal for a correctable
error, and the EDAC should be sent through the correction
cycle. The last three cases of double-bit errors will cause
the EDAC to signal LOWs on both ERR and MERR, which is
the interrupt indication for the CPU.
Error detection is accomplished as the 7-bit check word and
the 32-bit data word from memory are applied to internal
parity generators/checkers. If the parity of all seven group-
ings of data and check bits is correct, it is assumed that no
error has occurred and both error flags will be HIGH.
TABLE I. Write Control Function
Memory
Cycle
EDAC
Function
Control
S
1
DB Control
OEB
n
DB Output
Latch
LEDBO
CB
Error Flags
ERR
S
0
Data I/O
Check I/O
Control
OECB
MERR
Write
Generate
Check Word
L
L
Input
H
X
Output
Check Bit
*
L
H
H
*
See Table II for details of check bit generation.
3
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PDF描述 |
|---|---|
| 54F632 | 32-Bit Parallel Error Detection and Correction Circuit |
| 54F632DM | Error Detection & Correction (EDAC) |
| 54F632DMQB | Error Detection & Correction (EDAC) |
| 54F632DMQR | Error Detection & Correction (EDAC) |
| 54F632LM | Error Detection & Correction (EDAC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F632QC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:32-Bit Parallel Error Detection and Correction Circuit |
| 74F632VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:32-Bit Parallel Error Detection and Correction Circuit |
| 74F64 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-2-3-2-Input AND-OR-Invert Gate |
| 74F64 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F640 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal Bus Transceiver with 3-STATE Outputs |
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