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參數(shù)資料
| 型號： | 74ALVC16839 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 中文描述： | 低電壓20位可選注冊/容錯與3.6V的輸入和輸出緩沖區(qū) |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 81K |
| 代理商： | 74ALVC16839 |
2001 Fairchild Semiconductor Corporation
DS500713
www.fairchildsemi.com
December 2001
Revised December 2001
7
74ALVC16839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC16839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
Compatible with PC100 and PC133 DIMM module
specifications
I
1.65V to 3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(CLK to O
n
)
3.7 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
8.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVC16839MTD
Package Number
MTD56
Package Descriptions
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
I
0
–
I
19
O
0
–
O
19
CLK
Inputs
Outputs
Clock Input
REGE
Register Enable Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16839MTD | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74ALVC16839MTDX | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74ALVC16841 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs |
| 74ALVC16841APA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Integrated Device Technology Inc 功能描述: |
| 74ALVC16841DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Latch |
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