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參數(shù)資料
| 型號： | 74ALVC16841MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs |
| 中文描述： | ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 95K |
| 代理商： | 74ALVC16841MTD |
2001 Fairchild Semiconductor Corporation
DS500690
www.fairchildsemi.com
November 2001
Revised November 2001
7
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(D
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVC16841MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
LE
n
D
0
–
D
19
O
0
–
O
19
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16841MTD_Q | 功能描述:閉鎖 20-Bit Transparent L RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVC16841MTDX | 功能描述:閉鎖 Transparent Latch LV 20Bit 3.6V RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVC16952DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVC16952DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVC1G04DY | 制造商:Integrated Device Technology Inc 功能描述: |
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