- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375069 > 74ALVC16721MTD (FAIRCHILD SEMICONDUCTOR CORP) Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號(hào)： | 74ALVC16721MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | ALVC/VCX/A SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 82K |
| 代理商： | 74ALVC16721MTD |
2001 Fairchild Semiconductor Corporation
DS500691
www.fairchildsemi.com
October 2001
Revised October 2001
7
74ALVC16721
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16721 contains twenty non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications.
The 74ALVC16721 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16721 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.8V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(CLK to O
n
)
4.0 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
8.8 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVC16721MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
CLK
Clock Input
D
0
–
D
19
O
0
–
O
19
CE
Inputs
Outputs
Clock Enable Input (Active LOW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVC16839MTDX | Buffer/Flip-Flop |
| 74ALVC16839 | Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 74ALVC16839MTD | Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 74ALVC16841MTDX | 10-Bit D-Type Latch |
| 74ALVC16841 | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16721MTD_Q | 功能描述:觸發(fā)器 20-Bit D-Type Flip-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ALVC16721MTDX | 功能描述:觸發(fā)器 Transparent Latch LV 20Bit 3.6V RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ALVC16821 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs |
| 74ALVC16821MTD | 功能描述:觸發(fā)器 20-Bit D-Type Flip-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ALVC16821MTD_Q | 功能描述:觸發(fā)器 20-Bit D-Type Flip-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。