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參數資料
| 型號： | 74ALVC16601MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs |
| 中文描述： | ALVC/VCX/A SERIES, 18-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 74ALVC16601MTD |
2001 Fairchild Semiconductor Corporation
DS500682
www.fairchildsemi.com
October 2001
Revised October 2001
7
74ALVC16601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16601 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
OEAB is HIGH, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The ALVC16601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The ALVC16601 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(A to B, B to A)
3.4 ns max for 3.0V to 3.6V V
CC
4.0 ns max for 2.3V to 2.7V V
CC
7.0 ns max for 1.65V 1.95V V
CC
I
Power-down high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Order Number
74ALVC16601GX
(Note 2)
74ALVC16601MTD
(Note 3)
Package Number
BGA54A
(Preliminary)
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關PDF資料 |
PDF描述 |
|---|---|
| 74ALVC16721 | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 74ALVC16721MTDX | 20-Bit D-Type Flip-Flop |
| 74ALVC16721MTD | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 74ALVC16839MTDX | Buffer/Flip-Flop |
| 74ALVC16839 | Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74ALVC16601MTD_Q | 功能描述:總線收發(fā)器 18-Bit Universal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16601MTDX | 功能描述:總線收發(fā)器 UB Transceiver LV 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16623DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVC16623DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVC16646DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
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