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參數(shù)資料
| 型號(hào)： | 74ALVC16334DLRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 16位通用總線驅(qū)動(dòng)器，三態(tài)輸出 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大小： | 206K |
| 代理商： | 74ALVC16334DLRG4 |
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
Open
GND
R
L
R
L
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
V
OL
+ V
V
OH
V
0 V
V
I
0 V
0 V
t
w
V
I
V
I
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
V
LOAD
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
0 V
V
I
V
M
t
PHL
V
M
V
M
V
I
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
M
V
M
t
PLH
V
LOAD
V
LOAD
/2
1.8 V
2.5 V
±
0.2 V
2.7 V
3 V
±
0.3 V
1 k
500
500
500
V
CC
R
L
2
×
V
CC
2
×
V
CC
6 V
6 V
V
LOAD
C
L
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
V
CC
V
CC
2.7 V
2.7 V
V
I
V
CC
/2
V
CC
/2
1.5 V
1.5 V
V
M
t
r
/t
f
≤
2 ns
≤
2 ns
≤
2.5 ns
≤
2.5 ns
INPUT
SN74ALVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES128E–FEBRUARY 1998–REVISED SEPTEMBER 2004
Figure 1. Load Circuit and Voltage Waveforms
5
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