參數(shù)資料
型號(hào)： 74ALVCH16240TX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： BUFFER/DRIVER|QUAD|4-BIT|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC
中文描述： ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48
封裝： 6.10 MM, MO-153, TSSOP-48
文件頁(yè)數(shù)： 1/9頁(yè)
文件大小： 139K
代理商： 74ALVCH16240TX
SN74ALVCH16240
16-BIT
BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES045C – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V V
CC
operation.
The SN74ALVCH16240 is designed specifically
to improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer. It provides
inverting outputs and symmetrical active-low
output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16240 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
OUTPUT
Y
A
L
H
L
L
L
H
H
X
Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
DGG OR DL PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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