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參數(shù)資料
| 型號(hào)： | 74ABT16899 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 中文描述： | 18位鎖存器，16位奇偶發(fā)生器/檢查三態(tài) |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 105K |
| 代理商： | 74ABT16899 |
Philips Semiconductors
Product specification
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
2
1998 Feb 25
853-1960 19018
FEATURES
Symmetrical (A and B bus functions are identical)
Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
Independent transparent latches for A-to-B and B-to-A directions
Selectable ODD/EVEN parity
Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
Open-collector ERR output
Ability to simultaneously generate and check parity
Can simultaneously read/latch A and B bus data
Output capability: +64 mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power up 3-State
Power-up reset
Live insertion/extraction permitted
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with
separate transparent latches for the A bus and B bus. Either bus
can generate or check parity. The parity bit can be fed-through with
no change or the generated parity can be substituted with the SEL
input.
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
The 74ABT/H16899 features independent latch enables for the A
and B bus latches, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which
are outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations
of:
Transparent latch / 1 bus latched / both buses latched
Feed-through parity / generate parity
Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF; V
CC
= 5V
2.7
ns
t
PLH
t
PHL
Propagation delay
An to ERRA
C
L
= 50pF; V
CC
= 5V
5.0
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
4
pF
C
I/O
Output capacitance
Outputs disabled; V
O
= 0V or V
CC
7
pF
I
CCZ
Quiescent supply current
Outputs disabled; V
CC
=5.5V
500
μ
A
I
CCL
Output Low; V
CC
= 5.5V
10.5
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ABT16899 DL
BT16899 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ABT16899 DGG
BT16899 DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ABTH16899 DL
BH16899 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ABTH16899 DGG
BH16899 DGG
SOT364-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ABTH16899 | 18-bit latched transceiver with 16-bit parity generator/checker (3-State)(帶16位奇偶發(fā)生器/校驗(yàn)器的18位鎖存收發(fā)器（三態(tài)）) |
| 74ABT16899DGG | 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ABTH16899DGG | 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ABT20PWDH | Dual 4-input NAND gate |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ABT16899DGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ABT16899DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ABT16899DL,512 | 功能描述:總線收發(fā)器 18-BIT LATCH XCVR W/PARITY 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ABT16899DL,518 | 制造商:NXP Semiconductors 功能描述: |
| 74ABT16899DL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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