參數(shù)資料
型號(hào): 73S8014BN-ILR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: ROHS COMPLIANT, SOP-20
文件頁(yè)數(shù): 9/29頁(yè)
文件大小: 345K
代理商: 73S8014BN-ILR/F
DS_8014BN_057
73S8014BN Data Sheet
Rev. 1.0
17
3.6
On-Chip Oscillator and Card Clock
The 73S8014BN device has an on-chip oscillator that can generate the smart card clock using an external crystal
(connected between XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available
from another source it can be connected to XTALIN, and XTALOUT should be left unconnected.
For this device the card clock frequency can be chosen among four different division rates, defined by multiple-
state input CLKDIV, as per the following table:
CLKDIV
CLK
MAX
XTALIN/CLKIN
(MHz)
GND
1/4 XTALIN
27
VDD/3
XTALIN
20
VDD x 2/3
1/8 XTALIN
27
VDD
1/2 XTALIN
27
Note: The clock-divider ratio must be configured prior to activation and must not change during the card session.
Note: Special care should be taken when configuring the CLKDIV input when using the power-down mode. The
CLKDIV input does not contain an internal pullup or pulldown so it must not be allowed to be left unconnected. In
addition, the CLKDIV input should be set in such a manner as to set the voltage level to GND or VDD to keep the
current consumption to an absolute minimum.
There are numerous simple methods available to control CLKDIV as shown in Figure 5.
CLKDIV PIN
HOST I/O PIN
1. Selecting between Divide by 2 (I/O HIGH) or divide by 4 (I/O LOW)
CLKDIV PIN
HOST I/O PIN
2. Selecting between Divide by 2 (IO HIGH) or divide by 8 (IO LOW)
VDD
CLKDIV PIN
HOST I/O PIN 1
HOST I/O PIN 2
3. Selecting any of the four Divide ratios
R
2R
R
Figure 5: CLKDIV Usage
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