參數(shù)資料
型號: 73S8014BN-ILR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: ROHS COMPLIANT, SOP-20
文件頁數(shù): 26/29頁
文件大?。?/td> 345K
代理商: 73S8014BN-ILR/F
73S8014BN Data Sheet
DS_8014BN_057
6
Rev. 1.0
Table 1 provides the 73S8014BN pin names, pin numbers, type, equivalent circuits, and descriptions.
Table 1: 73S8014BN 20-Pin SO Pin Definitions
NAME
PIN
TYPE
EQUIVALENT
CIRCUIT
FIGURE #
DESCRIPTION
CARD INTERFACE
I/O
13
IO
Card I/O: Data Signal to/from Card. Includes an 11k
pullup
resistor to VCC.
C4
12
IO
Card C4: Data Signal to/from Card. Includes an 11k
pullup
resistor to VCC.
C8
14
IO
Card C8: Data Signal to/from Card. Includes an 11k
pullup
resistor to VCC.
RST
15
O
Card Reset. Provides reset (RST) signal to card.
CLK
17
O
Card Clock: Provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or frequency
of the external clock signal applied on XTALIN and CLKDIV
selections.
PRES
19
I
Card Presence Switch. Active high indicates the card is present.
Includes a high-impedance pulldown current source. The PRES
input includes a 5ms debounce for card insertion.
VCC
18
PSO
Card Power Supply. Logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
GND
16
GND
Card and Digital Ground
HOST PROCESSOR INTERFACE
CMDVCC
8
I
Command VCC (Negative Assertion). Logic-low on this pin causes
the LDO regulator to ramp the VCC supply to the card and initiates
a card activation sequence, only when a card is present.
5V/
3V
9
I
5V/3V/1.8V Card Selection. Logic-high selects 5V for VCC and
card interface. Logic-low selects 3V operation. Logic going from
high to low within
±400ns of CMDVCC falling selects 1.8V. When
the device is to be used with a single card voltage (3V or 5V only),
this pin should be connected to either GND or VDD. However, it
includes a high-impedance pullup resistor to default this pin high
(selection of 5V card) when not connected. Do not change the
level of this pin when
CMDVCC is low.
CLKDIV
6
I
Sets the Divide Ratio from the XTAL Oscillator (or External Clock
Input) to Card Clock. This is a multilevel input that uses a ratio of
the VDD voltage to select the clock divider as shown:
CLKDIV
CLOCK RATE
GND
XTALIN/4
VDD/3
XTALIN
VDD x 2/3
XTALIN/8
VDD
XTALIN/2
Note: This input has no internal pullup or pulldown so it must not
be left unconnected.
OFF
20
O
Active-Low Interrupt Signal to the Processor. Active-low
multifunction indicating fault conditions, device readiness, and
card presence. Open-drain output configuration. It includes an
internal 20k
pullup to V
DD.
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