參數(shù)資料
型號(hào): 73S8014BN-ILR/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: ROHS COMPLIANT, SOP-20
文件頁(yè)數(shù): 11/29頁(yè)
文件大?。?/td> 345K
代理商: 73S8014BN-ILR/F
DS_8014BN_057
73S8014BN Data Sheet
Rev. 1.0
19
CMDVCC
VCC
I/O
CLK
RSTIN
t
1
t
2
t
0
RST
t1 = 0.2 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t2 = RSTIN goes low and CLK becomes active
t3 = > 0.5s, CLK active, RST to become the copy of RSTIN
Figure 7: Activation Sequence—RSTIN High When
CMDVCC Goes Low
3.8
Deactivation Sequence
Deactivation is initiated either by the system controller by setting the
CMDVCC high or automatically in the event of
hardware faults. Hardware faults are overcurrent, VDD fault, VCC fault, and card extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the
CMDVCC high or OFF goes low due to a fault or card removal:
RST goes low at the end of t1.
CLK is set low at the end of t2.
I/O goes low at the end of t3. Out of reception mode.
VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR --
OFF
t1 = > 0.5s, timing by 1.5MHz internal oscillator
t2 = > 7.5s
t3 = > 0.5s
t4 = > 0.5s
t5 = depends on VCC filter capacitor
For NDS application, CF=1F makes t1 + t2 + t3 + t4 + t5 < 100s
Figure 8: Deactivation Sequence
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