參數(shù)資料
型號: 73S8010C-IM/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC32
封裝: 5 X 5 MM, LEAD FREE, QFN-32
文件頁數(shù): 5/27頁
文件大?。?/td> 348K
代理商: 73S8010C-IM/F
DS_8010C_024
73S8010C Data Sheet
Rev. 1.5
13
9
Deactivation Sequence
Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the
event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VCC fault, and
card extraction during the session.
The following steps and Figure 7 show the deactivation sequence and the timing of the card control
signals when the system controller clears the Start/Stop bit:
1. RST goes low at the end of t1.
2. CLK goes low at the end of t2.
3. I/O goes low at the end of t3. Out of reception mode.
4. Shut down VCC at the end of time t4.
Figure 7: Deactivation Sequence
10 Interrupt
The interrupt is an active low interrupt. It is set low if either a VCC fault or a VDD fault is detected. It is also
set low if one of the following status bit conditions is detected:
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
Figure 8: FAULT Functions,
INT operation
t1 ≥ 0.5 μs
t3 ≥ 0.5 μs
t2 ≥ 7.5 μs
t4 ≥ 0.5 μs
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
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