參數(shù)資料
型號: 72V3626L15PFG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝: GREEN, TQFP-128
文件頁數(shù): 7/36頁
文件大小: 349K
代理商: 72V3626L15PFG
15
IDT72V3626/72V3636/72V3646 CMOS 3.3V Triple Bus SyncFIFOTM
with Bus-Matching 256x36x2, 512x36x2, 1,024x36x2
COMMERCIALTEMPERATURERANGE
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
The data in a mail register remains intact after it is read and changes only
whennewdataiswrittentotheregister.TheEndianSelectfeaturehasnoeffect
on mailbox data.
NotethatMBCmustbeHIGHduringMasterReset(until
FFA/IRAand FFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail register and mail register flag timing diagrams, see Figure 28 and 29.
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format for
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the Port
CSizeSelect(SIZEC)inputdeterminesthePortCbussize.Theselevelsshould
bestaticthroughoutFIFOoperation.Bothbussizeselectionsareimplemented
at the completion of Master Reset, by the time the Full/Input Ready flag is set
HIGH, as shown in Figure 2 and 3.
Two different methods for sequencing data transfer are available for Ports
BandCregardlessofwhetherthebussizeselectionisbyte-orword-size.They
arereferredtoasBig-Endian(mostsignificantbytefirst)andLittle-Endian(least
significantbytefirst).ThelevelappliedtotheBig-EndianSelect(BE)inputduring
theLOW-to-HIGHtransitionof
MRS1andMRS2selectstheendianmethodthat
will be active during FIFO operation. This selection applies to both ports B and
C.TheendianmethodisimplementedatthecompletionofMasterReset,bythe
time the Full/Input Ready flag is set HIGH, as shown in Figure 2 and 3 (see
Endian Selection section).
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories
on these devices. Bus-Matching operations are done after data is read from
the FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port C).
The Endian select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections
limit the width of the data bus that can be used for mail register operations. In
this case, only those byte lanes belonging to the selected word- or byte-size
bus can carry mailbox data. The remaining data outputs will be indeterminate.
Theremainingdatainputswillbedon’tcareinputs.Forexample,whenaword-
size bus is selected on Port B, then mailbox data can be transmitted only from
A0-A17 to B0-B17. When a byte-size bus is selected on Port B, then mailbox
datacanbetransmittedonlyfromA0-A8toB0-B8.Similarly,whenaword-size
bus is selected on Port C, then mailbox data can be transmitted only from C0-
C17toA18-A35.Whenabyte-sizebusisselectedonPortC,thenmailboxdata
can be transmitted only from C0-C8 to A18-A26.
BUS-MATCHING FIFO1 READS
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.SincePort
B can have a byte or word size, only the first one or two bytes appear on the
selectedportionoftheFIFO1outputregister,withtherestofthelongwordstored
in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of
the long word to the FIFO1 output register in the order shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B9-B17 outputs
areindeterminate.
BUS-MATCHING FIFO2 WRITES
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary
registers. The CLKC rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs are
don't care inputs.
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