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參數(shù)資料
| 型號(hào)： | 72V3626L15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | GREEN, TQFP-128 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 349K |
| 代理商： | 72V3626L15PFG |
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COMMERCIALTEMPERATURERANGE
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
FULL/INPUT READY FLAGS (
FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (
FFAandFFC)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthantwo
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
nextmemorywritelocationhasbeenread.ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 20, 21, 22, and 23).
ALMOST-EMPTY FLAGS (
AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1for
AEBandregister
X2 for
AEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset,
programmed from Port A, or programmed serially (see the Almost-Empty flag
andAlmost-Fullflagoffsetprogrammingsection).AnAlmost-EmptyflagisLOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output register has been
read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level.AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (
AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
by the contents of register Y1 for
AFAandregisterY2forAFC.Theseregisters
are loaded with preset values during a FlFO reset, programmed from Port A,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Full flag is LOW when the number of words
in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the
IDT72V3626, IDT72V3636, or IDT72V3646 respectively. An Almost-Full flag
is HIGH when the number of words in its FIFO is less than or equal to [256-
(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3626, IDT72V3636, or
IDT72V3646 respectively. Note that a data word present in the FIFO output
register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or
lesswordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethereadthatreducedthenumberofwordsinmemoryto[256/512/1,024-
(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition
ofitssynchronizingclockaftertheFIFOreadthatreducesthenumberofwords
in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-
Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccursat
time tSKEW2 or greater after the read that reduces the number of words in
memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchronizing
clock cycle may be the first synchronization cycle (see Figure 26 and 27).
MAILBOX REGISTERS
EachFIFOhasan18-bitbypassregisterallowingthepassageofcommand
andcontrolinformationfromPortAtoPortBorfromPortCtoPortAwithoutputting
it in queue. The Mailbox Select (MBA, MBB and MBC) inputs choose between
a mail register and a FIFO for a port data transfer operation. The usable width
of both the Mail1 and Mail2 registers matches the selected bus size for ports B
and C.
WhensendingdatafromPortAtoPortBviatheMail1Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Register
when a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If
theselectedPortBbussizeis18bits,thentheusablewidthoftheMail1Register
employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the Mail1 Register
employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.)
WhensendingdatafromPortCtoPortAviatheMail2Register,thefollowing
isthecase: ALOW-to-HIGHtransitiononCLKCwritesdatatotheMail2Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or MBF2)
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, and RENB with MBB HIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9-B17
are indeterminate.)
The Mail2 Register Flag (
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.Thedatainamailregisterremainsintactafteritisreadandchangesonly
whennewdataiswrittentotheregister.Foran18-bitbussize,18bitsofmailbox
data appear on A18-A35. (In this case, A0-A17 are indeterminate.) For a 9-
bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case, A0-A17
and A27-A35 are indeterminate.)
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| 7305-0-15-15-47-14-04-0 | BRASS, GOLD FINISH, PCB TERMINAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72V3631L15PF | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲(chǔ)容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3631L15PF8 | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲(chǔ)容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3631L15PFG | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):有效 存儲(chǔ)容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3631L15PFG8 | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):有效 存儲(chǔ)容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3631L15PQF | 功能描述:IC SYNCFIFO 512X36 15NS 132QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲(chǔ)容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:132-BQFP 緩沖式 供應(yīng)商器件封裝:132-PQFP（24.13x24.13） 標(biāo)準(zhǔn)包裝:36 |
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