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參數(shù)資料
| 型號： | 72V3626L15PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | GREEN, TQFP-128 |
| 文件頁數(shù)： | 2/36頁 |
| 文件大小： | 349K |
| 代理商： | 72V3626L15PFG |
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10
COMMERCIALTEMPERATURERANGE
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT72V3626/72V3636/72V3646 undergoes a complete reset
by taking its associated Master Reset (
MRS1)inputLOWforatleastfourPort
A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The
FIFO2 memory undergoes a complete reset by taking its associated Master
Reset (
MRS2) input LOW for at least four Port A Clock (CLKA) and four Port
CClock(CLKC)LOW-to-HIGHtransitions. TheMasterResetinputscanswitch
asynchronouslytotheclocks. AMasterResetinitializestheassociatedreadand
writepointerstothefirstlocationofthememoryandforcestheFull/InputReady
flag(
FFA/IRA,FFC/IRC)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/
ORB) LOW, the Almost-Empty flag (
AEA,AEB)LOWandtheAlmost-Fullflag
(
AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(
MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraMasterReset,the
FIFO'sFull/InputReadyflagissetHIGHaftertwoWriteClockcycles. Thenthe
FIFO is ready to be written to.
ALOW-to-HIGHtransitionontheFIFO1MasterReset(
MRS1)inputlatches
the value of the Big-Endian (BE) input for determining the order by which bytes
aretransferredthroughPortsBandC. ItalsolatchesthevaluesoftheFlagSelect
(FS0, FS1) and Serial Programming Mode (
SPM) inputs for choosing the
Almost-FullandAlmost-Emptyoffsetprogrammingmethod.
A LOW-to-HIGH transition on the FIFO2 Master Reset (
MRS2)clearsthe
flagoffsetregistersofFIFO2(X2,Y2). ALOW-to-HIGHtransitionontheFIFO2
Master Reset (
MRS2) together with the FIFO1 Master Reset input (MRS1)
latchesthevalueoftheBig-Endian(BE)inputforPortsBandCandalsolatches
the values of the Flag Select (FS0, FS1) and Serial Programming Mode (
SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method (for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Fullflagoffsetprogrammingsection). TherelevantMasterResettiming
diagrams can be found in Figure 4 and 5.
NotethatMBCmustbeHIGHduringMasterReset(until
FFA/IRAandFFC/
IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master Reset.
PARTIAL RESET (
PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking
its associated Partial Reset (
PRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memoryundergoesalimitedresetbytakingitsassociatedPartialReset(
PRS2)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGHtransitions.ThePartialResetinputscanswitchasynchronously
to the clocks. A Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (
FFA/IRA,FFC/IRC)LOW,theEmpty/Output
Ready flag (
EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (
AFA, AFC) HIGH. A Partial Reset also forces
the Mailbox Flag (
MBF1, MBF2)oftheparallelmailboxregisterHIGH.Aftera
PartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClock
cycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Resetisinitiated,thosesettingswill remainunchangeduponcompletionofthe
resetoperation.APartialResetmaybeusefulinthecasewherereprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
writtentoPortCorreadfromPortB.Thisselectiondeterminestheorderbywhich
bytes (or words) of data are transferred through those ports. For the following
illustrations, note that both ports B and C are configured to have a byte (or a
word) bus size.
A HIGH on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
ALOWontheBE/
FWFTinputwhentheMasterReset(MRS1,MRS2)inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
PortCfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
— TIMING MODE SELECTION
AfterMasterReset,theFWFTselectfunctionisavailable,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through(FWFT)mode.OncetheMasterReset(
MRS1, MRS2)inputisHIGH,
aHIGHontheBE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA
(for FIFO1) and CLKC (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA,EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFC)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytothedata
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
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| 72V3631L15PF | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3631L15PF8 | 功能描述:IC SYNCFIFO 512X36 15NS 120-TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3631L15PFG | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:45 |
| 72V3631L15PFG8 | 功能描述:IC FIFO SYNC 512X36 15NS 120TQFP 制造商:idt, integrated device technology inc 系列:72V 包裝:帶卷（TR） 零件狀態(tài):有效 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:120-LQFP 供應(yīng)商器件封裝:120-TQFP（14x14） 標(biāo)準(zhǔn)包裝:750 |
| 72V3631L15PQF | 功能描述:IC SYNCFIFO 512X36 15NS 132QFP 制造商:idt, integrated device technology inc 系列:72V 包裝:托盤 零件狀態(tài):過期 存儲容量:18K（512 x 36） 功能:同步 數(shù)據(jù)速率:66.7MHz 訪問時(shí)間:10ns 電壓 - 電源:3 V ~ 3.6 V 電流 - 電源（最大值）:400μA 總線方向:雙向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:132-BQFP 緩沖式 供應(yīng)商器件封裝:132-PQFP（24.13x24.13） 標(biāo)準(zhǔn)包裝:36 |
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