- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294128 > 72T3655L5BBGI (INTEGRATED DEVICE TECHNOLOGY INC) 2K X 36 OTHER FIFO, 3.6 ns, PBGA208 PDF資料下載
參數(shù)資料
| 型號： | 72T3655L5BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 36 OTHER FIFO, 3.6 ns, PBGA208 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 18/57頁 |
| 文件大小： | 472K |
| 代理商： | 72T3655L5BBGI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
marked location. During retransmit mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges,
REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN) and RCLK.
AfterMasterReset,FWFT/SIactsasaserialinputforloading
PAEandPAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedvia
ASYW,this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,the
FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating
HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (
WEN)
Whenthe
WENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR will go
LOW allowing a write to occur. The
IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedvia
ASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,the
EF/OR,PAE
and
HF flagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
the
HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the
REN and RCSinputs
mustbetiedLOW.The
OEinputisusedtoprovideAsynchronouscontrolofthe
three-stateQnoutputs.
WRITE CHIP SELECT (
WCS)
The
WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the
WCS must be enabled, held
LOW.
READ ENABLE (
REN)
When Read Enable is LOW, data is loaded from the RAM array into the
outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using
REN provided that
RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
(
EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
FIFO is empty. Once a write is performed,
EF will go HIGH allowing a read to
occur. The
EFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
cycle. Both
RCS and REN must be active, LOW for data to be read out on the
rising edge of RCLK.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write.
RENandRCSdonotneedtobeassertedLOW fortheFirst
Word to fall through to the output register. In order to access all other words,
a read must be executed using
REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (
OR)
will go HIGH with a true read (RCLK with
REN=LOW;RCS=LOW),inhibiting
further read operations.
REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then
REN
must be held active, (tied LOW).
SERIAL ENABLE (
SEN )
The
SENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.
SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGH transition of SCLK.
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE (
OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
datafromtheoutputregister. When
OEisHIGH,theoutputdatabus(Qn)goes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 72V275L15PF8 | 32K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 72V285L10PF8 | 64K X 18 OTHER FIFO, 6.5 ns, PQFP64 |
| 72V285L15TFI9 | 64K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 72V3626L15PFG | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 72V3684L15PF | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72T3655L5BBI | 功能描述:IC FIFO 2048X36 5NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:83MHz，200MHz 訪問時間:10ns，3.6ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15 |
| 72T3655L6-7BB | 功能描述:IC FIFO 2048X36 6-7NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:66MHz，150MHz 訪問時間:12ns，3.8ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15 |
| 72T3665L4-4BB | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72T3665L4-4BBG | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72T3665L5BB | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。