參數(shù)資料
型號(hào)： 72T3655L5BBGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 2K X 36 OTHER FIFO, 3.6 ns, PBGA208
封裝： 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-208
文件頁數(shù)： 13/57頁
文件大?。?/td> 472K
代理商： 72T3655L5BBGI
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
# of Bits Used:
10 bits for the IDT72T3645
11 bits for the IDT72T3655
12 bits for the IDT72T3665
13 bits for the IDT72T3675
14 bits for the IDT72T3685
15 bits for the IDT72T3695
16 bits for the IDT72T36105
17 bits for the IDT72T36115
18 bits for the IDT72T36125
Note: All unused bits of the
LSB & MSB are don’t care
5907 drw07
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
12
13
14
15
16
17
11
Interspersed
Parity
17
10
1
8
D/Q35
D/Q19
9
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
2nd Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
12
13
14
15
16
17
11
Interspersed
Parity
17
10
1
8
9
IDT72T3645/55/65/75/85/95/105/115/125
x36 Bus Width
Non-Interspersed
Parity
Non-Interspersed
Parity
D/Q35
D/Q19
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Data Inputs/Outputs
# of Bits Used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
2nd Parallel Offset Write/Read Cycle
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (LSB) REGISTER (PAF)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q8
16
D/Q17
D/Q16
IDT72T3645/55/65/75/85/95/105
x18 Bus Width
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Data Inputs/Outputs
# of Bits Used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EMPTY OFFSET (MSB) REGISTER (PAE)
Data Inputs/Outputs
17
16
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (LSB) REGISTER (PAF)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (MSB) REGISTER (PAF)
17
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q8
16
17
D/Q17 D/Q16
D/Q17
D/Q16
D/Q17 D/Q16
IDT72T36115/72T36125
x18 Bus Width
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF)
1
2
3
4
5
6
7
8
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
17
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF)
9
10
11
12
13
14
15
16
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
17
FULL OFFSET REGISTER (PAF)
IDT72T36115/72T36125
x9 Bus Width
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE)
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF)
1
2
3
4
5
6
7
8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF)
9
10
11
12
13
14
15
16
IDT72T3645/55/65/75/85/95/105
x9 Bus Width
NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
相關(guān)PDF資料
PDF描述
72V275L15PF8 32K X 18 OTHER FIFO, 10 ns, PQFP64
72V285L10PF8 64K X 18 OTHER FIFO, 6.5 ns, PQFP64
72V285L15TFI9 64K X 18 OTHER FIFO, 10 ns, PQFP64
72V3626L15PFG 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
72V3684L15PF 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72T3655L5BBI 功能描述:IC FIFO 2048X36 5NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲(chǔ)容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:83MHz，200MHz 訪問時(shí)間:10ns，3.6ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15
72T3655L6-7BB 功能描述:IC FIFO 2048X36 6-7NS 208-BGA 制造商:idt, integrated device technology inc 系列:72T 包裝:托盤 零件狀態(tài):過期 存儲(chǔ)容量:72K（2K x 36） 功能:異步，同步 數(shù)據(jù)速率:66MHz，150MHz 訪問時(shí)間:12ns，3.8ns 電壓 - 電源:2.375 V ~ 2.625 V 電流 - 電源（最大值）:70mA 總線方向:單向 擴(kuò)充類型:深度，寬度 可編程標(biāo)志支持:是 中繼能力:是 FWFT 支持:是 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BGA 供應(yīng)商器件封裝:208-PBGA（17x17） 標(biāo)準(zhǔn)包裝:15
72T3665L4-4BB 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72T3665L4-4BBG 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72T3665L5BB 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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