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參數(shù)資料
| 型號： | 71V35781S183PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 632K |
| 代理商： | 71V35781S183PF |
6.42
20
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and
TRST.
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number.
IDT Device ID (27:12)
0x23C, 0x23E
Defines IDT part number 71V35761SA and 71V35781SA, respectively.
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register.
I5301 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
0100
RESERVED
0101
RESERVED
0110
RESERVED
0111
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
1000
RESERVED
Same as above.
1001
RESERVED
1010
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5301 tbl 04
Available JTAG Instructions
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| 71V3578S133PF | 制造商:Integrated Device Technology Inc 功能描述:SRAM CHIP SYNC SINGLE 3.3V 4.5M-BIT 256K X 18 4.2NS - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 71V3578S133PF, SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 4.2ns 100-Pin TQFP |
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| 71V3578S133PFG8 | 功能描述:靜態(tài)隨機存取存儲器 256Kx18 SYNC 3.3V FLOW-THROUGH 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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