參數(shù)資料
型號(hào): 71V35781S183PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 18 CACHE SRAM, 3.3 ns, PQFP100
封裝: 14 X 20 MM, PLASTIC, TQFP-100
文件頁(yè)數(shù): 10/22頁(yè)
文件大?。?/td> 632K
代理商: 71V35781S183PF
6.42
18
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
CLK
ADSP
GW,BWE,BWx
CE, CS1
CS0
ADDRESS
ADSC
DATAOUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
5301 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW,
ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW,
ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles,
ADSP and ADSC have different limitations.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
5301 drw 15
,
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