參數(shù)資料
型號: 71V35761YSA183BGI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 CACHE SRAM, 3.3 ns, PBGA119
封裝: BGA-119
文件頁數(shù): 9/22頁
文件大?。?/td> 621K
代理商: 71V35761YSA183BGI8
6.42
17
IDT71V35761Y (128K x 36), IDT71V35781Y (256K x 18), 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
tC
Y
C
tS
S
tC
L
tC
H
tH
A
tS
A
tS
C
tH
C
tO
E
tO
L
Z
tH
S
C
L
K
A
D
S
P
A
D
S
C
A
D
R
E
S
G
W
C
E
,C
S
1
A
D
V
D
A
T
A
O
U
T
O
E
Z
S
in
g
le
R
e
a
d
S
n
o
z
e
M
o
d
e
tZ
Z
P
W
6
4
5
d
rw
1
2
O
1
(A
x
)
A
x
(N
o
te
4
)
tZ
Z
R
A
z
,
NOTES:
1.
Device
must
power
up
in
deselected
Mode
2.
LBO
is
Don't
Care
for
this
cycle.
3.
Itis
not
necessary
to
retain
the
state
of
the
input
registers
throughout
the
Power-down
cycle.
4.
C
S
0timing
transitions
are
identical
but
inverted
to
the
CE
and
CS
1signals.
For
example,
when
CE
and
CS1
are
LOW
on
this
waveform,
CS
0is
HIGH.
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