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參數(shù)資料
| 型號： | 71V35761YSA183BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 3.3 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 621K |
| 代理商： | 71V35761YSA183BGI8 |
6.42
12
IDT71V35761Y (128K x 36), IDT71V35781Y (256K x 18), 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
200MHz(5)
183MHz
166MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
5
—
5.5
—
6
—
ns
tCH(1)
Clock High Pulse Width
2
—
2.2
—
2.4
—
ns
tCL(1)
Clock Low Pulse Width
2
—
2.2
—
2.4
—
ns
Output Parameters
tCD
Clock High to Valid Data
—
3.1
—
3.3
—
3.5
ns
tCDC
Clock High to Data Change
1.0
—
1.0
—
1.0
—
ns
tCLZ(2)
Clock High to Output Active
0
—
0
—
0
—
ns
tCHZ(2)
Clock High to Data High-Z
1.5
3.1
1.5
3.3
1.5
3.5
ns
tOE
Output Enable Access Time
—
3.1
—
3.3
—
3.5
ns
tOLZ(2)
Output Enable Low to Output Active
0
—
0
—
0
—
ns
tOHZ(2)
Output Enable High to Output High-Z
—
3.1
—
3.3
—
3.5
ns
Set Up Times
tSA
Address Setup Time
1.2
—
1.5
—
1.5
—
ns
tSS
Address Status Setup Time
1.2
—
1.5
—
1.5
—
ns
tSD
Data In Setup Time
1.2
—
1.5
—
1.5
—
ns
tSW
Write Setup Time
1.2
—
1.5
—
1.5
—
ns
tSAV
Address Advance Setup Time
1.2
—
1.5
—
1.5
—
ns
tSC
Chip Enable/Select Setup Time
1.2
—
1.5
—
1.5
—
ns
Hold Times
tHA
Address Hold Time
0.4—
0.5—
ns
tHS
Address Status Hold Time
0.4
—
0.5
—
0.5
—
ns
tHD
Data In Hold Time
0.4—
0.5—
ns
tHW
Write Hold Time
0.4—
0.5—
ns
tHAV
Address Advance Hold Time
0.4
—
0.5
—
0.5
—
ns
tHC
Chip Enable/Select Hold Time
0.4—
0.5—
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
—
100
—
100
—
ns
tZZR(3)
ZZ Recovery Time
100
—
100
—
100
—
ns
tCFG(4)
Configuration Set-up Time
20
—
22
—
24
—
ns
6445 tbl 16
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the
LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 71V3576S133BGI | 制造商:Integrated Device Technology Inc 功能描述: |
| 71V3576S133PFG | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3576S133PFG8 | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3576S133PFGI | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V3576S133PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4.2ns 100-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 4.2NS 100TQFP - Tape and Reel |
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