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參數(shù)資料
| 型號： | 71V2556XSA166BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, PBGA119 |
| 封裝： | GREEN, BGA-119 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556XSA166BGI8 |
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
17
tHE
tSE
R/
W
A
1
A
2
CLK
CEN
ADV/
LD
ADDRESS
CE
1
,
CE
2
(2)
BW
1
-
BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)
Q(A
6
)
Q(A
7
)
tCD
Read
tCHZ
4875
drw
08
Write
tCLZ
D(A
2
)
D(A
4
)
tCDC
D(A
5
)
Write
tCH
tCL
tCYC
tHW
tSW
tHA
tSA
A
4
A
3
tHC
tSC
tSD
tHD
tHADV
tSADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
tHB
tSB
OE
Read
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
D
(A
2)
represents
the
input
data
to
the
SRAM
corresponding
to
address
A
2.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Individual
Byte
Write
signals
(
BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
two
cycles
before
the
actual
data
is
presented
to
the
SRAM.
Timing Waveform of Combined Read and Write Cycles (1,2,3)
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