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參數(shù)資料
| 型號： | 71V2556XSA166BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, PBGA119 |
| 封裝： | GREEN, BGA-119 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556XSA166BGI8 |
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
19
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
D
(A
3)
represents
the
input
data
to
the
SRAM
corresponding
to
address
A
3.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
CEN
when
sampled
high
on
the
rising
edge
of
clock
will
block
that
L-H
transition
of
the
clock
from
propogating
into
the
SRAM.
The
part
will
behave
as
ifthe
L-H
clock
transition
did
not
occur.
All
internal
registers
in
the
SRAM
will
retain
their
previous
state.
4.
Individual
Byte
Write
signals
(BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
two
cycles
before
the
actual
data
is
presented
to
the
SRAM.
R/
W
A1
CLK
ADV/
L
D
ADDRESS
O
E
DATA
OUT
Q(A
1
)
tCD
tCLZ
tCHZ
tCDC
tCH
tCL
tHC
tSC
tSD
tHD
A
5
A
3
tSB
DATA
IN
tHE
tSE
A
2
tHA
tSA
A
4
tHW
tSW
tHB
C
E
N
tHADV
tSADV
4875
drw
10
Q(A
2
)
Q(A
4
)
D(A
3
)
B
W
1
-
B
W
4
C
E
1,
C
E
2
(2)
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