參數(shù)資料
型號： 71M6543G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 59/157頁
文件大小： 2178K
代理商： 71M6543G-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
151
6.8.2
71M6543 Analog Pins
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent
circuit, as specified in Section 6.8.4.
Table 113: 71M6543 Analog Pins
Pin
Name
Type
Circuit
Function
87
86
IADC0
IADC1
I
6
Differential or Single-Ended Analog Line Current Sense
Inputs. These pins are voltage inputs to the internal A/D
converter. Typically, they are connected to the outputs of
current sensors. Unused pins must be connected to
V3P3A.
When configured as differential inputs (i.e., by setting the
DIFFx_E control bits, where x = 0, 2, 4, 6) pins are paired to
form differential inputs pairs: IADC0-IADC1, IADC2-IADC3,
IADC4-IADC5, and IADC6-IADC7.
IADC2-IADC3, IADC4-IADC5, and IADC6-IADC7 can be
configured for communication with the 71M6xx3 remote
isolated sensor interface (i.e., by setting the RMTx_E
control bits, where x = 2, 4, 6). When configured as remote
sensor interfaces, these pins form balanced digital pairs for
bidirectional digital communications with a 71M6xx3
remote isolated sensor.
68
67
IADC2
IADC3
66
65
IADC4
IADC5
64
63
IADC6
IADC7
84
VADC8 (VA)
I
6
Line Voltage Sense Inputs. These pins are voltage inputs
to the internal A/D converter. Typically, they are connected
to the outputs of resistor dividers. Unused pins must be
connected to V3P3A.
83
VADC9 (VB)
82
VADC10 (VC)
88
VREF
O
9
Voltage Reference for the ADC. This pin should be left
unconnected (floating).
75
XIN
I
8
Crystal Inputs. A 32 kHz crystal should be connected
across these pins. Typically, a 15 pF capacitor is also
connected from XIN to GNDA and a 10 pF capacitor is
connected from XOUT to GNDA. It is important to
minimize the capacitance between these pins. See the
crystal manufacturer data sheet for details. If an external
clock is used, a 150 mV (p-p) clock signal should be
applied to XIN, and XOUT should be left unconnected.
76
XOUT
O
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