參數(shù)資料
型號(hào)： 71M6543G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 133/157頁
文件大?。?/td> 2178K
代理商： 71M6543G-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
77
Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events:
Wake-up timer timeout.
Pushbutton (PB) is activated.
A rising edge on SEGDIO4, SEGDIO52 or SEGDIO55.
Activity on the RX or OPT_RX pins.
The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4
Wake-Up Behavior for details.
Table 62 shows the circuit functions available in each operating mode.
Table 62: Available Circuit Functions
Circuit Function
System Power
Battery Power
MSN (Mission Mode)
BRN (Brownout Mode)
LCD
SLEEP
PLL_FAST=1
PLL_FAST=0
PLL_FAST=1
PLL_FAST=0
CE (Computation Engine)
Yes
--
1
--
FIR
Yes
--
ADC, VREF
Yes
--
PLL
Yes
Boost
2
--
Battery Measurement
Yes
--
Temperature sensor
Yes
Max MPU clock rate
4.92MHz
(from PLL)
1.57MHz
(from PLL)
4.92MHz
(from PLL)
1.57MHz
(from PLL)
--
MPU_DIV clk. divider
Yes
--
ICE
Yes
--
DIO Pins
Yes
--
Watchdog Timer
Yes
--
LCD
Yes
--
LCD Boost
Yes
EEPROM Interface (2-wire)
Yes
--
EEPROM Interface (3-wire)
Yes
--
UART (full speed)
Yes
--
Optical TX modulation
38.4kHz
38.9kHz
38.4kHz
38.9kHz
--
Flash Read
Yes
--
Flash Page Erase
Yes
--
Flash Write
Yes
--
RAM Read and Write
Yes
--
Wakeup Timer
Yes
OSC and RTC
Yes
DRAM data preservation
Yes
--
NV RAM data preservation
Yes
Notes:
1.
“--“ indicates that the corresponding circuit is not active
2.
“Boost” implies that the LCD boost circuit is active (i.e., LCD_VMODE[1:0] = 10 (I/O RAM 0x2401[7:6])). The LCD boost
circuit requires a clock from the PLL to function. Thus, the PLL is automatically kept active if LCD boost is active while in
LCD mode, otherwise the PLL is de-activated.
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