參數(shù)資料
型號： 71M6543G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 130/157頁
文件大?。?/td> 2178K
代理商： 71M6543G-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
74
2008–2011 Teridian Semiconductor Corporation
v1.2
Table 61: TMUX2[4:0] Selections
TMUX2[4:0]
Signal Name
Description
0
WD_OVF
Indicates when the watchdog timer has expired (overflowed).
1
PULSE_1S
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 1 second
interval. Multiple cycles should be averaged together to filter out
jitter.
2
PULSE_4S
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 second
interval. Multiple cycles should be averaged together to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 second pulse.
3
RTCLK
32.768 kHz clock waveform
8
SPARE[1] bit – I/O RAM
0x2704[1]
Copies the value of the bit stored in 0x2704[1]. For general
purpose use.
9
SPARE[2] bit – I/O RAM
0x2704[2]
Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
A
WAKE
Indicates when a WAKE event has occurred.
B
MUX_SYNC
Internal multiplexer frame SYNC signal. See Figure 4 and Figure
C
MCK
See 2.5.3 on page 50.
E
GNDD
Digital GND. Use this signal to make the TMUX2OUT pin static.
12
INT0 – DIG I/O
Interrupt 0. See 2.4.9 on page 40. Also see Figure 12 on page 46.
13
INT1 – DIG I/O
14
INT2 – CE_PULSE
15
INT3 – CE_BUSY
16
INT4 - VSTAT
17
INT5 – EEPROM/SPI
18
INT6 – XFER, RTC
1F
RTM_CK (flash)
See 2.3.5 on page 26.
Note:
All
TMUX2[4:0] values which are not shown are reserved.
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