參數(shù)資料
型號(hào)： 71M6541G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁數(shù)： 157/165頁
文件大?。?/td> 2208K
代理商： 71M6541G-IGT/F
v1.1
2008–2011 Teridian Semiconductor Corporation
91
3.5
Data Flow and MPU/CE Communication
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 30. In a typical
application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA,
IB, etc., performing calculations to measure active power (Wh), reactive power (VARh), A
2h, and V2h
for four-quadrant metering. These measurements are then accessed by the MPU, processed further and
output using the peripheral devices available to the MPU.
Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM.
The CE outputs a total of six discrete signals to the MPU. These consist of four pulses and two interrupts:
CE_BUSY
XFER_BUSY
WPULSE, VPULSE (pulses for active and reactive energy)
XPULSE, YPULSE (auxiliary pulses)
These interrupts are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY
indicates that the CE is actively processing data. This signal occurs once every multiplexer cycle (typically
396 s), and indicates that the CE has updated status information in its CESTATUS register (CE RAM 0x80).
XFER_BUSY indicates that the CE is updating data to the output region of the RAM. This indication
occurs whenever the CE has finished generating a sum by completing an accumulation interval
determined by SUM_SAMPS[12:0], I/O RAM 0x2107[4:0], 2108[7:0], (typically every 1000 ms). Interrupts to
the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
WPULSE and VPULSE are typically used to signal energy accumulation of real (Wh) and reactive (VARh)
energy. Tying WPULSE and VPULSE into the MPU interrupt system can support pulse counting.
XPULSE and YPULSE can be used to signal events such as sags and zero crossings of the mains voltage
to the MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the
CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing
events.
Figure 30: MPU/CE Data Flow
Refer to 5.3 CE Interface Description for additional information on setting up the device using the MPU
firmware.
MPU
CE
I/O RAM (Configuration RAM)
Pulses
Samples
WPULSE
VPULSE
XPULSE
YPULSE
Control
Processed
Metering
Data
MUX
Control
Interrupts
CECONFIG
CESTATUS
XRAM
CE_BUSY
XFER_BUSY
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