參數(shù)資料
型號： 71M6541G-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： LEAD FREE, LQFP-64
文件頁數(shù)： 148/165頁
文件大?。?/td> 2208K
代理商： 71M6541G-IGT/F
v1.1
2008–2011 Teridian Semiconductor Corporation
83
3.2.1
BRN Mode
In BRN mode, most non-metering digital functions are active (as shown in Table 67) including ICE, UART,
EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN
mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU
frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power.
From BRN mode, the MPU can choose to enter LCD or SLP modes. When system power is restored
while the 71M654x is in BRN mode, the part automatically transitions to MSN mode.
The recommended minimum power configuration for BRN mode is as follows:
RCE0 = 0x00 (I/O RAM 0x2709[7:0]) - remote sensors disabled
LCD_BAT = 1 (I/O RAM 0x2402[7]) - LCD powered from VBAT
LCD_VMODE[1:0] = 0 (I/O RAM 0x2401[7:6]) - 5V LCD boost disabled
CE6 = 0x00 (I/O RAM 0x2106) - CE, RTM and CHOP are disabled
MUX_DIV[3:0] = 0 (I/O RAM 0x2100[7:4]) - the ADC multiplexer is disabled
ADC_E = 0 (I/O RAM 0x2704[4]) - ADC disabled
VREF_CAL = 0 (I/O RAM 0x2704[7]) – Vref not driven out
VREF_DIS = 1 (I/O RAM 0x2704[6]) - Vref disabled
PRE_E = 0 (I/O RAM 0x2704[5] - pre-amp disabled
BCURR = 0 (I/O RAM 0x2704[3]) - battery 100A current load OFF
TMUX[5:0] = 0x0E (I/O RAM 0x2502[5:0]) – TMUXOUT output set to a dc value
TMUX2[4:0] = 0x0E (I/O RAM 0x2503[4:0]) – TMUXOUT2 output set to a dc value
CKGN = 0x24 (I/O RAM 0x2200) - PLL set slow, MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) set to maximum
TEMP_PER[2:0] = 6 (I/O RAM 0x28A0[2:0]) - temp measurement set to automatic every 512 s
TEMP_BSEL = 1 (I/O RAM 0x28A0[7]) - temperature sensor monitors VBAT
PCON = 1 (SFR 0x87) - at the end of the main BRN loop, halt the MPU and wait for an interrupt
The baud rate registers are adjusted as desired
All unused interrupts are disabled
3.2.2
LCD Mode
LCD mode may be commanded by the MPU at any time by setting the LCD_ONLY control bit (I/O RAM
0x28B2[6]). However, it is recommended that the LCD_ONLY control bit be set by the MPU only after the
71M654x has entered BRN mode. For example, if the 71M654x is in MSN mode when LCD_ONLY is set,
the duration of LCD mode is very brief and the 71M654x immediately 'wakes'.
In LCD mode, V3P3D is disabled, thus removing all current leakage from the VBAT pin. Before asserting
LCD_ONLY mode, it is recommended that the MPU minimize PLL current by reducing the output
frequency of the PLL to 6.2 MHz (i.e., write PLL_FAST = 0, I/O RAM 0x2200[4]). The LCD boost system
requires a clock from the PLL for its operation. Thus, if the LCD boost system is enabled (i.e.,
LCD_VMODE[1:0] = 10, I/O RAM 0x2401[7:6]), then the PLL is automatically kept active during LCD
mode, otherwise the PLL is de-activated.
In LCD mode, the data contained in the LCD_SEG registers is displayed using the segment driver pins.
Up to two LCD segments connected to the pins SEGDIO22 and SEGDIO23 can be made to blink without
the involvement of the MPU, which is disabled in LCD mode. To minimize battery power consumption,
only segments that are used should be enabled.
After the transition from LCD mode to MSN or BRN mode, the PC (Program Counter) is at 0x0000, the
XRAM is in an undefined state, and configuration I/O RAM bits are reset (see Table 76 for I/O RAM state
upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded
locations in Table 76 are non-volatile).
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