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| 型號(hào)： | 71M6534-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 封裝： | LEAD FREE, LQFP-120 |
| 文件頁(yè)數(shù)： | 45/124頁(yè) |
| 文件大?。?/td> | 2008K |
| 代理商： | 71M6534-IGTR/F |
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FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
27
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are
programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable commu-
nication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated. Table 16
shows the selectable UART operation modes.
Table 15: Baud Rate Generation
Using Timer 1
(WDCON[7] = 0)
Using Internal Baud Rate Generator
(WDCON[7] = 1)
UART0
2
smod * f
CKMPU/ (384 * (256-TH1))
2
smod * f
CKMPU/(64 * (2
10-S0REL))
UART1
N/A
fCKMPU/(32 * (2
10-S1REL))
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
SMOD is the SMOD bit in the SFR PCON register. TH1 is the high byte of timer 1.
Table 16: UART Modes
UART 0
UART 1
Mode 0
N/A
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Mode 1
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
Mode 2
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
N/A
Mode 3
Start bit, 8 data bits, parity, stop bit, va-
riable baud rate (internal baud rate ge-
nerator or timer 1)
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant
1. 8-bit serial modes with parity can be simulated by setting and reading the 9
th bit, using the
control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON and S1CON SFRs for transmit
and RB81 (S1CON[2]) for receive operations.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake sig-
nals for inter-processor communication in multi-processor systems. In this case, the slave processors
have bit SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master proces-
sor outputs the slave’s address, it sets the 9
th bit to 1, causing a serial port receive interrupt in all the
slaves. The slave processors compare the received byte with their address. If there is a match, the ad-
dressed slave will clear SM20 or SM21 and receive the rest of the message. The rest of the slave’s will
ignore the message. After addressing the slave, the host outputs the rest of the message with the 9
th bit
set to 0, so no additional serial port receive interrupts will be generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
The UARTs require software to clear the interrupt bits. It is recommended to use bit manipulation instruc-
tions rather than byte instructions when using UART1 in full duplex mode. For example, the CLR TI0 in-
struction should be used instead of ANL #0FDH,S0CON. Further measures in code involve reducing and
combining the write operations to S1CON and reducing the time between the read and write operations on
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