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| 型號： | 71M6534-IGT/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP120 |
| 封裝： | LEAD FREE, LQFP-120 |
| 文件頁數(shù)： | 13/124頁 |
| 文件大?。?/td> | 2008K |
| 代理商： | 71M6534-IGT/F |
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FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
11
cal assignment of values for the SLOTn_SEL and SLOTn_ALTSEL registers assuming seven time slots
(MUX_DIV = 7) for the processing of three voltage and current phases plus an additional neutral current.
The correlation between signal numbers, CE memory addresses, and analog signals is given in Table 3.
For the processing of three voltage and current phases in a typical poly-phase meter without neutral
measurement, MUX_DIV is set to 6, and SLOT6_SEL as well as SLOT6_ALTSEL would be empty.
Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV = 7)
Time Slot
Regular Slot
Alternate Slot
Register
Typical Selections
Register
Typical Selections
Signal
Number
Signal for
ADC
Signal
Number
Signal for
ADC
0
SLOT0_SEL
0
IA
SLOT0_ALTSEL
A
TEMP
1
SLOT1_SEL
1
VA
SLOT1_ALTSEL
1
VA
2
SLOT2_SEL
2
IB
SLOT2_ALTSEL
B
VBAT
3
SLOT3_SEL
3
VB
SLOT3_ALTSEL
3
VB
4
SLOT4_SEL
4
IC
SLOT4_ALTSEL
4
IC
5
SLOT5_SEL
5
VC
SLOT5_ALTSEL
5
VC
6
SLOT6_SEL
6
ID
SLOT6_ALTSEL
6
ID
SLOT7_SEL
–
SLOT7_ALTSEL
SLOT8_SEL
–
SLOT8_ALTSEL
SLOT9_SEL
–
SLOT9_ALTSEL
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN. Each multiplexer state will start on the rising edge of CK32. FIR conversions
require 1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN.
1.2.3
A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The
resolution of the ADC is programmable using the I/O RAM registers M40MHZ and M26MHZ (see Table 2).
Table 2: ADC Resolution
Setting for [M40MHZ,
M26MHZ]
FIR_LEN
FIR CE Cycles
Resolution
[00], [10] or [11]
0
1
2
138
288
384
18 bits
21 bits
22 bits
[01]
0
1
2
186
384
588
19 bits
22 bits
24 bits
Initiation of each ADC conversion is controlled by MUX_CTRL as described above. At the end of each ADC
conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX selection.
1.2.4
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multip-
lexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of
each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multip-
lexer selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits.
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| 71M6534-IGTR/F | 功能描述:計(jì)量片上系統(tǒng) - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6541D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:71M6541D/71M6541F/71M6541G/71M6542F/71M6542G 是 TeridianTM 的第4 代高集成度單相電表SoC |
| 71M6541D_1111 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Energy Meter ICs |
| 71M6541D-IGT/F | 功能描述:計(jì)量片上系統(tǒng) - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6541D-IGTR/F | 功能描述:計(jì)量片上系統(tǒng) - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
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