參數(shù)資料
型號： 71M6534-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP120
封裝： LEAD FREE, LQFP-120
文件頁數(shù)： 117/124頁
文件大?。?/td> 2008K
代理商： 71M6534-IGT/F
71M6533/71M6534 Data Sheet
FDS_6533_6534_004
92
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
4.3.4
Environment
Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by
implementing the following steps:
Load the CE data into RAM.
Establish the equation to be applied in EQU.
Establish the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES.
Establish the number of cycles per ADC multiplexer frame (MUX_DIV).
Apply proper values to SLOTn_SEL and SLOTn_ALTSEL.
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see Figure 18 in the System
Timing Summary section). This means that the product of the number of cycles per frame and the num-
ber of conversions per frame must be 12 (allowing for one settling cycle). The default configuration is
FIR_LEN = 0 (two cycles per conversion) and MUX_DIV = 6 (6 conversions per mux cycle).
4.3.5
CE Calculations
Table 48: CE EQU Equations and Element Input Mapping
EQU
Watt & VAR Formula
(WSUM/VARSUM)
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
W2SUM/
VAR2SUM
I0SQ
SUM
I1SQ
SUM
I2SQ
SUM
0*
VA IA
(1 element, 2W 1
φ)
VA*IA
–
IA
–
1*
VA*(IA-IB)/2
(1 element, 3W 1
φ)
VA*(IA-IB)/2
–
IA-IB
IB
–
2*
VA*IA + VB*IB
(2 element, 3W 3
φ Delta)
VA*IA
VB*IB
–
IA
IB
–
3*
VA*(IA-IB)/2 + VC*IC
(2 element, 4W 3
φ Delta)
VA*(IA-IB)/2
–
VC*IC
IA-IB
IB
IC
4*
VA*(IA-IB)/2 + VB*(IC-IB)/2
(2 element, 4W 3
φ Wye)
VA*(IA-IB)/2 VB*(IC-IB)/2
–
IA-IB
IC-IB
IC
5
VA*IA + VB*IB + VC*IC
(3 element, 4W 3
φ Wye)
VA*IA
VB*IB
VC*IC
IA
IB
IC
* Only EQU = 5 is supported by CE code version CE34A02D.
4.3.6
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through B shown in
Table 49: CE Raw Data Access Locations
Name
Address
Description
CE
MPU
Type
IA FIR data
0x00
Input
ADC Input data, valid at the end of the
MUX frame. The address mapping of ana-
log inputs to memory is hard-wired in the
ADC converter circuit.
VA FIR data
0x01
0x04
Input
IB FIR data
0x02
0x08
Input
VB FIR data
0x03
0x0C
Input
IC FIR data
0x04
0x10
Input
VC FIR data
0x05
0x14
Input
ID FIR data
0x06
0x18
Input
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