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參數(shù)資料
| 型號： | 7134SA35PB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 8 DUAL-PORT SRAM, 35 ns, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | 7134SA35PB |
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
OE or CE.
3. R/
W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
ADDRESS
DATAOUT
PREVIOUS DATA VALID
DATA VALID
tOH
tAA(5)
tRC
2720 drw 08
2720 drw 09
CE
DATAOUT
VALID DATA
(4)
tPD
tAOE
(4)
tACE
OE
tHZ
(2)
tLZ
(1)
tLZ
(1)
tPU
50%
ICC
ISB
CURRENT
tHZ
(2)
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