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參數(shù)資料
| 型號(hào)： | 7134SA35PB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 8 DUAL-PORT SRAM, 35 ns, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | 7134SA35PB |
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
10
Truth Table I – Read/Write Control
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by
CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (
CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (
OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)
NOTES:
1. R/
W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a
CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of
CE or R/W going HIGH to the end-of-write cycle.
4. If the
CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (
CE or R/W) is asserted last.
NOTE:
1. A0L - A11L
≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance
Left or Right Port(1)
R/
W
CE
OE
D0-7
Function
X
H
X
Z
Port Deselected and in Power-Down
Mode, ISB2 or ISB4
XH
X
Z
CER = CEL = H, Power Down
Mode ISB1 or ISB3
LL
X
DATAIN
Data on port written into memory
HL
L
DATAOUT
Data in memory output on port
X
H
Z
High impedance outputs
2720 tbl 11
2720 drw 12
R/
W
tWC
ADDRESS
DATAIN
CE
tDW
tWR
(3)
tDH
tEW
(2)
tAW
tAS
(5)
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