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參數(shù)資料
| 型號： | 70V3319S133BCGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 4.2 ns, CBGA256 |
| 封裝： | 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 222K |
| 代理商： | 70V3319S133BCGI |
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
5
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables(6)
R/
WL
R/
WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A17L(1)
A0R - A17R(1)
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLKR
Clock
PIPE/
FTL(5)
PIPE/
FTR(5)
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
REPEATL
REPEATR
Counter Repeat(4)
UBL
UBR
Upper Byte Enable (I/O9-I/O17)(6)
LBL
LBR
Lower Byte Enable (I/O0-I/O8)(6)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(2)
OPTL
OPTR
Option for selecting VDDQX(2,3)
VDD
Power (3.3V)(2)
VSS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5623 tbl 01
1.
A17 is a NC for IDT70V3399.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When
REPEATX is asserted, the counter will reset to the last valid address loaded
via
ADSX.
5. PIPE/
FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/
FT = VIH, i.e., the
signals take two cycles to deselect.
NOTES:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70V3319S133BCI | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S133BCI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 15NS/4.2NS 256BGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S133BF | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S133BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 15NS/4.2NS 208CABGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S133BFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 15ns/4.2ns 208-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 15NS/4.2NS 208CABGA - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
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