參數(shù)資料
型號(hào)： 70V25L25PFGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 8K X 16 DUAL-PORT SRAM, 25 ns, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 2/25頁(yè)
文件大?。?/td> 211K
代理商： 70V25L25PFGI
6.42
IDT70V35/34S/L
(IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
10
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first,
CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE
, tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
tRC
R/
W
CE
ADDR
tAA
OE
UB, LB
5624 drw 08
(4)
tACE
(4)
tAOE
(4)
tABE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
70V35/34X15
Com'l Only
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Unit
Symbol
Parameter
Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time(3)
____
15
____
20
____
25
ns
tABE
Byte Enable Access Time(3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time(3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
ns
tPU
Chip Enable to Power Up Time (1,2)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)10
____
10
____
10
____
ns
tSAA
Semaphore Address Access(3)
____
15
____
20
____
25
ns
5624 tbl 11
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