參數(shù)資料
型號(hào)： 70V25L25PFGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 8K X 16 DUAL-PORT SRAM, 25 ns, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 17/25頁(yè)
文件大小： 211K
代理商： 70V25L25PFGI
6.42
IDT70V35/34S/L
(IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
24
semaphore request latch. The critical case of semaphore timing is when
both sides request a single token by attempting to write a zero into it at the
same time. The semaphore logic is specially designed to resolve this
problem.Ifsimultaneousrequestsaremade,thelogicguaranteesthatonly
one side receives the token. If one side is earlier than the other in making
therequest,thefirstsidetomaketherequestwillreceivethetoken.Ifboth
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port
SRAM. Say the 8K x 18 SRAM was to be divided into two 4K x 18 blocks
which were to be dedicated at any one time to servicing either the left or
right port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be defined
as the indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port SRAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 4K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port SRAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
a transfer and the I/O device cannot tolerate any wait states. With the use
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
their assigned portions of memory continuously without any wait states.
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processorreadsanincompletedatastructure,amajorerrorconditionmay
exist. Therefore, some sort of arbitration must be used between the two
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpretingprocessortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
D
5624 drw 20
0
D
Q
WRITE
D0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
RPORT
SEMAPHORE
READ
SEMAPHORE
READ
,
Figure 4.
IDT70V35/34 (IDT70V25/24) Semaphore Logic
相關(guān)PDF資料
PDF描述
70V34S20PFGI 4K X 18 DUAL-PORT SRAM, 20 ns, PQFP100
710-405J12 STEEL, CIRCULAR ADAPTER
710-405J16 STEEL, CIRCULAR ADAPTER
710-405J24 STEEL, CIRCULAR ADAPTER
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70V25L25PFGI8 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Kx16, 3.3V DUAL- PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V25L25PFI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Kx16, 3.3V DUAL- PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V25L25PFI8 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Kx16, 3.3V DUAL- PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V25L35G 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 128KBIT 8KX16 35NS 84PIN PGA - Trays
70V25L35J 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 128KBIT 8KX16 35NS 84PLCC - Rail/Tube
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